1. Field of the Invention
The present invention relates to a microprocessor and a method thereof for controlling a clock signal, and more particularly, to a microprocessor and a method thereof for controlling a clock signal related to a power-down mode.
2. Description of the Prior Art
The prior art 8051 microcontroller architecture and 8052 microcontroller architecture are both produced by Intel(copyright). The prior art microcontroller (microprocessor) is widely used as a control unit for many devices. It is well-known that the microprocessor itself is capable of performing power management including an idle mode and a power-down mode for reducing power consumption. Please refer to FIG. 1, which is a circuit diagram of a prior art microprocessor 20. The microprocessor 20 is electrically connected to an external clock generator 10. The clock generator 10 has an oscillator 12 (a crystal oscillator for example), and two capacitors 14 used to stabilize the clock signal outputted from the oscillator 12. The microprocessor 20 has a logic circuit 22, an interrupt control unit 24, an idle mode control unit 26, and a power-down mode control unit 28. The logic circuit 22 is used to perform a predetermined logic operation. The interrupt control unit 24 is used for receiving an external interrupt signal Int to activate a corresponding interrupt service routine (ISR). The idle mode control unit 26 is used to control operation of the idle mode including timing for activating the idle mode and terminating the idle mode. The idle mode control unit 26 has a flip-flop 30, and two logic gates 32, 34. The flip-flop 30 functions as a storage device used for holding a control bit IDL. That is, the logic value (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) of the control bit IDL is used to determine whether the microprocessor 20 enters the idle mode or not. The power-down mode control unit 28 is used to control operation of the power-down mode including timing for activating the idle mode and terminating the power-down mode. The power-down mode control unit 28 has a flip-flop 36 and a logic gate 38. The flip-flop 36 functions as a storage device used for holding a control bit PD. That is, the logic value (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) of the control bit PD is used to determine whether the microprocessor 20 enters the power-down mode or not. In addition, a hardware reset signal Rst is inputted into the, microprocessor 20 for resetting the microprocessor 20 to an initial state. For example, with regard to a walkie-talkie device that adopts the microprocessor 20 as a micro control unit (MCU), a user can press a power button of the walkie-talkie device to shut down the walkie-talkie device. Therefore, the walkie-talkie device begins entering the power-down mode. If the user wants to use the walkie-talkie device later, the user then presses the power button of the walkie-talkie device again to force a power supply device such as batteries to provide the walkie-talkie device with a proper operating voltage. At the same time, the hardware reset signal Rst is transmitted to the microprocessor 20 for forcing the microprocessor 20 to enter the initial state. Operation of the prior art microprocessor 20 is briefly described as follows. For instance, the initial states of the hardware reset signal Rst and the interrupt signal Int both correspond to a high logic value xe2x80x9c1xe2x80x9d. When a hardware reset event or an interrupt event is triggered, the corresponding hardware reset signal Rst or the interrupt signal Int will transit from the initial high logic value xe2x80x9c1xe2x80x9d to the low logic value xe2x80x9c0xe2x80x9d. In addition, when the control bit IDL corresponds to the low logic value xe2x80x9c0xe2x80x9d, the control bit IDL is further transmitted to the logic gate 34 through the flip-flop 30. The logic gate 34 performs an NAND logic operation. When there is one input port corresponding to the low logic value xe2x80x9c0xe2x80x9d, an output port of the logic gate 34 will keep the high logic value xe2x80x9c1xe2x80x9d. Because another input port of the logic gate 34 is used to receive the clock signal generated from the clock generator 10, the clock signal is gated by the logic gate 34 from driving the logic circuit 22. It is well-known that the microprocessor 20 uses an edge-trigger means, and works properly according to the clock signal. Therefore, the logic circuit 22 stops working and interrupts current running logic operation without the driving clock signal. That is, the logic gate 34 functions as a clock control unit for controlling the clock signal inputted into the logic circuit 22. At the same time, the microprocessor 20 enters the idle mode. Even though the microprocessor 20 enters the idle mode, the clock signal generated from the clock generator 10 still drives the interrupt control unit 24. If an interrupt event occurs and triggers the interrupt signal Int to transit from the initial high logic value xe2x80x9c1xe2x80x9d to the low logic value xe2x80x9c0xe2x80x9d, the interrupt control unit 24 accordingly outputs a signal with the low logic value xe2x80x9c0xe2x80x9d to the logic gate 32, which performs an AND logic operation, for resetting the control bit IDL. That is, the control bit IDL corresponds to the original high logic value xe2x80x9c1xe2x80x9d. At the same time, the interrupt control unit 24 will activate a corresponding ISR. From an operation result of the logic gate 34, it is obvious that the clock signal is capable of driving the logic circuit 22. After the ISR is finished, the interrupt control unit 24 informs the logic circuit 22 to continue running the interrupted logic operation caused by the idle mode. In other words, the idle mode will be terminated after the interrupt event occurs. The control bit PD is an input port of the logic gate 38. When the control bit PD is set by the low logic value xe2x80x9c0xe2x80x9d, the logic gate 38, which performs an NAND logic operation, will keep its output port at the high logic value xe2x80x9c1xe2x80x9d. The clock signal generated from the clock generator 10 that connected to the logic gate 38 is gated by the logic gate 38. After a period of time, the clock generator 10 stops generating the clock signal, and is no longer capable of driving the microprocessor 20. That is, the logic gate 38 functions as a clock control unit for control clock signal inputted into the microprocessor 20. When a hardware reset event occurs for restarting the microprocessor 20 to its initial state, the hardware reset signal Rst transits from original high logic value xe2x80x9c1xe2x80x9d to a low logic value xe2x80x9c0xe2x80x9d. The flip-flop 36 simultaneously reset the control bit PD by the initial high logic value xe2x80x9c1xe2x80x9d. Therefore, the microprocessor 20 escapes from the power-down mode.
As mentioned above, when the microprocessor 20 enters the idle mode, the logic circuit 22 interrupts current running logic operation owing to the required clock signal being cut. However, operational data related to the unfinished logic operation are kept in buffers, and the operational data can be accessed by the interrupted logic operation after the idle mode is terminated. Because the logic circuit 22 cannot work without the clock signal, the power consumption of the microprocessor 20 is reduced under the idle mode. In order to revive the microprocessor 20, the interrupt control unit 24 plays a key role. Under the idle mode, the clock signal generated from the clock generator 10 still drives the interrupt control unit 24. Therefore, when an interrupt event occurs to trigger the interrupt signal Int, the running interrupt control unit 24 is capable of rescuing the microprocessor 20 from the idle mode. The logic circuit 22, therefore, can continue running the logic operation previously interrupted by the idle mode. However, the clock generator 10 continuously generates the clock signal under the idle mode. During the execution of the idle mode, the clock generator 10 consumes much power, and the running circuit element such as the interrupt control unit still driven by the clock signal 24 consumes much power as well. On the contrary, with regard to the power-down mode of the microprocessor 20, the clock generator 10 stops outputting the clock signal. All of the circuit elements driven by the clock signal are interrupted. In other words, overall power consumption is greatly reduced under the power-down mode. However, the important difference between the idle mode and the power-down mode is that the microprocessor 20 entering the power-down mode cannot revive to continue running the interrupted logic operation. In other words, if the hardware reset event is activated to rescue the microprocessor 20 from the power-down mode, the microprocessor 20 regains its initial setting by flushing current data stored in buffers. The power-down mode compared with the idle mode is capable of saving much more power, but the microprocessor 20 cannot finish the interrupted logic operation to acquire a desired result after termination of the power-down mode.
It is therefore a primary objective of the claimed invention to provide a method for controlling a clock signal when a corresponding microprocessor enters a power-down mode. According to the claimed invention, the microprocessor can continue running the interrupted logic operation after the power-down mode is terminated.
According to the claimed invention, a method for controlling a clock signal of a microprocessor is disclosed. The microprocessor is connected to a clock generator, and the clock generator generates the clock signal for driving the microprocessor. The microprocessor has a clock control unit, a first control unit, and a second control unit. The clock control unit is electrically connected to the clock generator for controlling whether the clock generator outputs the clock signal to the microprocessor. The first control unit is electrically connected to the clock control unit, and the first control unit generates a level-trigger and outputs a first control signal to the clock control unit when receiving an interrupt signal inputted into the microprocessor. The second control unit is electrically connected to the clock control unit, and the second control unit outputs a second control signal to the clock control unit when the microprocessor enters a power-down mode. The method includes (a) the second control unit outputting the second control signal to the clock control unit for disabling the clock generator from generating the clock signal to the microprocessor so as to activate the power-down mode; and after performing step (a), inputting the interrupt signal to the first control unit for driving the first control unit to generate the level-trigger and driving the first control unit to output the first control signal to the clock generator so as to restart the clock generator to generate the clock signal.
The claimed invention further provides a microprocessor. The microprocessor is connected to a clock generator, and the clock generator generates a clock signal for driving the microprocessor. The microprocessor has a clock control unit, a first control unit, and a second control unit. The clock control unit is electrically connected to the clock generator for controlling whether the clock generator outputs the clock signal to the microprocessor. The first control unit is electrically connected to the clock control unit, and the first control unit generates a level-trigger and outputs a first control signal to the clock control unit when receiving an interrupt signal inputted into the microprocessor. The second control unit is electrically connected to the clock control unit, and the second control unit outputs a second control signal to the clock control unit when the microprocessor enters a power-down mode. The second control unit is capable of outputting the second control signal to the clock control unit for disabling the clock generator from generating the clock signal to the microprocessor so as to activate the power-down mode, and the first control unit is capable of receiving the interrupt signal for driving the first control unit to generate the level-trigger and driving the first control unit to output the first control signal to the clock generator so as to restart the clock generator to generate the clock signal.
It is an advantage over the prior art that the claimed invention not only has low power consumption because of entering the prior art power-down mode, but also can continue running the interrupted logic operation after the power-mode is ended. In conclusion, the claimed microprocessor has the advantage of the prior art power-down mode for greatly reducing power consumption and the advantage of the prior art idle mode for continuing the interrupted operation after the idle mode is ended.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.